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Description: 这是异步FIFO的VHDL实现代码，已经在FPGA上通过实践证明，运行状态良好
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Size: 20434 |
Author: 杨宇 |
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Description: 用Verilog语言写的FPGA FIFO，仅供参考。
Platform: |
Size: 1765 |
Author: yangyu |
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Description: 介绍异步FIFO的概念、应用及其结构，分析实现异步FIFO的难点问题及其解决办法；在传统设计的基础上提出一种新颖的电路结构并对其进行综合仿真和FPGA实现。
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Size: 169984 |
Author: sht816dzkd@163.com |
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Description: 并口的EPP协议，与外部的FIFO的empty,full信号共同控制数据传输-of EPP parallel port agreement with the external FIFO empty, full common control signal data transmission
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Size: 1024 |
Author: 陈刚 |
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Description: 这是从opencores下的fifo代码,包括了异步和同步的,还有写的testbench,希望对大家有用.-This is opencores fifo under the code, including asynchronous and synchronous. There testbench written in the hope that useful for all.
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Size: 20480 |
Author: daiowen |
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Description: 8位相等比较器，比较8位数是否相等
-- 8-bit Identity Comparator
-- uses 1993 std VHDL
-- download from www.pld.com.cn & www.fpga.com.cn-eight other phase comparators, Comparing the same whether the median 8-- 8-bit Identity Comparator-- uses 1993 std VHDL-- download from www.pld.com.cn
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Size: 1024 |
Author: 罗兰 |
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Description: 邵舒渊等编《SOPC系统设计入门教程》，简单明了，入门方便-edited "SOPC Design Portal Guide," simple, convenient portal
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Size: 5891072 |
Author: 高超 |
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Description: 基于FPGA的异步FIFO的软硬件实现,通过VERILOG编程实现后下载到FPGA芯片-FPGA-based hardware and software asynchronous FIFO to achieve, through the Verilog programming downloaded to the FPGA chip after
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Size: 241664 |
Author: youren |
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Description: 本原代码中利用VHDL语言编写了RAM、FIFO、ROM等常用的存储和缓冲部件，完全的代码在ALTERA的FPGA上已经通过仿真测试，保证可用.-primitive code using VHDL prepared RAM, FIFO, ROM, and other commonly used storage and buffer components, complete code in the Altera FPGA simulation test has been passed to ensure that available.
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Size: 2048 |
Author: nick |
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Description: FIFO（先进先出队列）通常用于数据的缓存和用于容纳异步信号的频率或相位的差异。本FIFO的实现是利用
双口RAM 和读写地址产生模块来实现的.FIFO的接口信号包括异步的写时钟（wr_clk）和读时钟（rd_clk）、
与写时钟同步的写有效（wren）和写数据（wr_data） 、与读时钟同步的读有效（rden）和读数据（rd_data）
为了实现正确的读写和避免FIFO的上溢或下溢，给出与读时钟和写时钟分别同步的FIFO的空标志（empty）和
满标志（full）以禁止读写操作。-FIFO (FIFO queue) is usually used for data caching and asynchronous signal used to accommodate the frequency or phase differences. The realization of this FIFO is to use dual-port RAM and to read and write address generator module achieved. FIFO interface signals, including asynchronous write clock (wr_clk) and read clock (rd_clk), and write effectively write clock synchronization (wren) and write data (wr_data), clock synchronization and time effective reading (rden) and read data (rd_data) in order to realize the right to read and write and to avoid FIFO overflow or the underflow, is given with the time clock and write clock synchronization FIFO respectively empty signs (empty) and full logo (full) to prohibit the read and write operations.
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Size: 378880 |
Author: lsg |
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Description: cmos数据到fifo再到usb的fifo部分程序(68013a)-cmos data to fifo the fifo to the usb part of the procedures (68013a)
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Size: 158720 |
Author: |
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Description: fpga嵌入式系统组件，可以很方便的扩展，是个实例的例子，可以实现歌曲播放-FPGA embedded system components, it is easy to expand, is an example of the example, you can realize music player
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Size: 14336 |
Author: dahai |
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Description: FPGA向SRAM中写入数据(VHDL编程)，包含通用fifo，sram等-FPGA to the SRAM write data (VHDL programming), contains general fifo, sram, etc.
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Size: 270336 |
Author: 王刚 |
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Description: 一篇关于FIFO设计以及FPGA设计的文章-FIFO 1 on the design and FPGA design article
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Size: 453632 |
Author: Roger |
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Description: alteral FPGA VERILOG 利用 ROM DCFIFO 和RAM
实现高速到低速时钟域的数据传输 ，值得学习。-alteral FPGA VERILOG using ROM DCFIFO and RAM to realize high-speed low-speed clock domain data transfer, it is worth learning.
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Size: 928768 |
Author: alison |
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Description: para13：
fifo.vhd FIFO（双口RAM）
fifo1.vhd FIFO（嵌入式EAB）
fifo2.vhd FIFO（LPM）-para13: fifo.vhd FIFO (dual port RAM) fifo1.vhd FIFO (embedded EAB) fifo2.vhd FIFO (LPM)
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Size: 3072 |
Author: libing |
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Description: DM642 接硬盘的方案，利用FPGA作FIFO缓冲，达到数据/图像/视频的实时高速写入。-DM642 access the hard disk of the program, the use of FPGA for FIFO buffer to data/images/video real-time high-speed write.
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Size: 2846720 |
Author: 李东平 |
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Description: 基于高速数字信号处理器(DSP) 和大规模现场可编程门阵列( FPGA) ,成功地研制了小型
化、低功耗的实时视频采集、处理和显示平台. 其中的DSP 负责图像处理,其外围的全部数字逻辑功能都集成在一片FPGA 内,包括高速视频流FIFO、同步时序产生与控制、接口逻辑转换和对视频编/ 解码器进行设置的I2 C 控制核等. 通过增大FIFO 位宽、提高传输带宽,降低了占用EMIF 总线的时间 利用数字延迟锁相环逻辑,提高了显示接口时序控制精度. 系统软件由驱动层、管理层和应用层组成,使得硬件管理与算法程序设计彼此分离,并能协同工作. 系统中的图像缓冲区采用了
三帧的配置方案,使得该平台最终具有对PAL/ N TSC 两种制式的全分辨率彩色复合视频信号进行实时采集、显示和处理的能力.-Based on high-speed digital signal processor (DSP) and large-scale field programmable gate array (FPGA), successfully developed a smaller, low-power real-time video capture, processing and display platform. One of the DSP is responsible for image processing, all its external digital logic functions are integrated in a FPGA, including high-speed video streaming FIFO, synchronous sequential generate and control, conversion and interface logic for video encoder/decoder to set up the control of nuclear and other I2 C. through increased FIFO bit width, increase the transmission bandwidth, reducing the time occupied by EMIF bus delay phase-locked loop using digital logic,
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Size: 546816 |
Author: John |
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Description: 这是异步fifo的vhdl实现代码，已经在FPGA上通过实践证明，运行状态良好-This is the asynchronous fifo realize the VHDL code has been adopted in the FPGA Practice has proved that running in good condition
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Size: 1024 |
Author: xzq |
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